The present invention relates to methods and apparatus for controlling static random access memory (SRAM), and in particular for reducing the power dissipation of the SRAM based on the data stored therein.
SRAM memory cells store data in the form of complementary low voltage and high voltage at opposite sides of the cell. An SRAM, unlike dynamic random access memory (DRAM), maintains the data content of the memory calls as long as power is applied to the cell. DRAM memory cells, on the other hand, are periodically refreshed with the stored data content. An SRAM cell includes a “true” node associated with a bit line (BLT) of the SRAM memory and a complementary node associated with a complementary bit line (BLC) of the SRAM memory. When the true node is read as a high voltage, the value of the SRAM memory cell is digital one. If the true node is read as a low voltage, the value of the SRAM memory cell is a digital zero.
During write and read cycles, a conventional SRAM memory system will employ a pre-charge circuit to drive the bit line BLT and the complementary bit line BLC to a power supply voltage of the SRAM memory, Vdd, before data is written to the memory cell. During the time that the data is actually written to the SRAM memory cell, a write buffer drives the bit line BLT and the complementary bit line BLC. During the read operation, the active components of the SRAM memory cell itself will drive the bit line BLT, which is sensed (using so-called evaluation circuitry) to determine the value of the stored data bit in the cell.
The conventional circuitry for accessing (or evaluating) the contents of each memory cell via the bit line BLT includes combinational logic and/or transistor circuitry to mirror the stored data value onto a global bit line (GBL). The conventional evaluation circuitry includes a portion for charging the GLB and a portion for interfacing a respective BLT line to the GBL. Thus, the conventional evaluation circuitry includes a plurality of interface portions (one portion for each BLT of a word line) and a single charging portion for the word line. The conventional evaluation circuitry is operable such that during read or write operations the GBL swings (particularly during a write data=0 operation) and clocking circuitry of the charging portions is active, thereby consuming AC power. Thus, the power dissipation (particularly during successive write cycles) is significant.
The power dissipation problem becomes significantly worse as the frequency of the clock increases and the size of the SRAM increases, which is an ongoing circumstance as higher and higher memory performance remains a design goal. Accordingly, there is a need in the art for a new approach to controlling SRAM memory cells in order to counteract the increase in power dissipation resulting from higher and higher clock frequencies and larger and larger SRAM memories.